The present invention relates to a method for designing cell layout and a cell layout design program of semiconductor integrated circuit. More particularly, the present invention relates to a method for designing cell layout and a cell layout design program which obtain a layout result satisfying a circuit delay restriction, in a short time period with a little piece of command information.
In a conventional method for designing cell layout of semiconductor integrated circuit, it has been important that delay be considered in layout processing. Particularly, as a method for designing cell layout with a logic having a data flow (hereinafter referred to as data path), for example, a technique disclosed in Japan Patent Laid-open No. 2000-250964 is known. This conventional technique groups cells using the same arrangement information as a key by giving in advance relative positional information to each cell, and temporarily arranges cells of the same group in a specified order. Subsequently, the technique vertically or horizontally moves the above-mentioned temporarily arranged cells to array them, thus reducing the wiring length to satisfy the delay restriction.